The present invention relates to operations in flash memory devices. More particularly, the present invention relates to a method and apparatus to diminish undesirable programming in a flash memory device.
Flash memory devices have proven to be important memory elements in the past several years, and industry pundits predict an ever-increasing role for such devices in the future. A great advantage flash memory devices have over typical EPROM""s and EEPROM""s are, respectively, system programmability and lower cost.
Despite the many advantages of flash memories over other memories, flash memory devices have several opportunities for improvement. For example, flash memories in their typical implementations suffer from the problems of xe2x80x9covererased memory cellsxe2x80x9d and xe2x80x9cwild cellsxe2x80x9d which result in all memory cells not behaving exactly alike with respect to their electrical behavior. In fact, many flash memory devices include wide variations of electrical behavior between adjacent memory cells.
Overerased memory cells are particularly undesirable. Overerased memory cells arise when a block of memory cells is erased. Because of the behavioral dissimilarities of the memory cells within the block, one memory cell typically takes longer to erase than other memory cells. As a result, this memory cell defines the erasure time for all memory cells in the block.
Erasing the block for the defined erasure time results in some memory cells being overerased. Overerased memory cells are memory cells that were erased for an excessive period of time. Overerased memory cells have an undesirable large positive charge on their floating gate. For example, an overerased memory cell will have a floating gate voltage of 3V. A non-overerased memory cell will typically have a floating gate voltage of 0.5V. As a result, overerased memory cells operate in the depletion mode. Hence, overerased memory cells conduct current through a bit line to which they are coupled even when the overerased cells are biased with zero drain voltages.
Thus, selected programmed memory cells, coupled to the same bit line as an overerased memory cell, will appear to draw current and appear to be erased. Therefore, data stored in the flash memory devices may not be accurately read. Therefore, overerased memory cells are preferably corrected.
Typically, overerased memory cells are corrected, by applying a gate voltage of 12 volts to the entire block of memory cells. As the floating gate voltage of such memory cells becomes sufficiently lower to come out of depletion mode. With the gate of the overerased cells sufficiently higher than normally erased cells, the control gate couples the floating gate even higher, through a tunnelling mechanism in the channel or source area. Electrons are pulled to the floating gate, and lower the voltage of the floating gate. However, during the aforementioned process, since the procedure affects all of the cells in the block, some non-overerased memory cells become undesirably programmed. Therefore, there is a need to correct overerased memory cells while avoiding undesired programming of non-overerased memory cells.
The present invention provides a method of erasing a memory cell, including the step of erasing a memory cell. The current in the memory cell is measured. If the measured memory cell current approximately exceeds a predetermined level, the memory cell is soft programmed so if the memory cell is not overerased, the memory cell is undisturbed. The memory cell is soft programmed until the measured memory cell current is less than or equal to the predetermined level.
In one embodiment, the memory cell is soft programmed for approximately 100 microseconds. In another embodiment, the predetermined level is 10 microamps. In yet another embodiment, the present invention includes the step of applying a gate voltage between approximately 6 and 7 volts, and a drain voltage of approximately 5 volts to a memory cell.
In another embodiment, the present invention provides a state machine, controlling soft programming of a memory cell, that includes a distribution adjustment group. The distribution adjustment group includes a read column state for ascertaining whether overerased cells exist in a column. An increment column state, coupled to the read column state, selects a next column. A soft program row state, coupled to the read column state, corrects an overerased memory cell while not disturbing a non-overased memory cell. An increment row state, coupled to the soft program row and read column states, selects a memory cell in a subsequent row.
In yet a further embodiment, the present invention provides a memory, including a memory cell array including blocks of memory cells, and a command execution logic module. A state machine, coupled to the command execution logic module, controls soft programming of a memory cell in the memory cell array. An X-interface circuit is coupled to the state machine. A Y-interface circuit is coupled to the state machine. The state machine includes a distribution adjustment group that comprises a read column state. An increment column state is coupled to the read column state. A soft program row state, in which a non-overerased memory cell is undisturbed, is coupled to the read column state. An increment row state is coupled to the soft program row and read column states. In another embodiment, as system may be formed by coupling the memory to a memory controller.